The present invention relates generally to data processing systems, and more particularly, to analyzing the test coverage of an electrical circuit given a plurality of test inputs.
In U.S. Pat. No. 5,604,895, a method for inserting computer code into a high level language (HLL) software model of an electrical circuit to monitor test coverage of the software model when exposed to test inputs is disclosed. This method has the following drawbacks: it generates an augmented description code of the electrical circuit by which the test coverage is to be determined and the augmented description code will occupy some computer storage space; executing the augmented description code by a simulation software or hardware tool generates additional dump file(s) that will occupy some additional computer storage space; determining the test coverage will incur the cost of using a simulation software or hardware tool; determining the test coverage by using a simulation software or hardware tool is time consuming; and rerunning the simulation software is necessary if the test coverage of other variables is going to be determined.
To avoid the drawbacks of the prior art method for analyzing the test coverage of a high level language (HLL) software model of an electrical circuit when exposed to test inputs, the inventors of the present invention contemplated that the dump file(s) generated by a simulation software or hardware tool can be used in analyzing the test coverage of a software model when exposed to test inputs.
It is therefore an object of the present invention to provide a method and system for analyzing the test coverage of a software model when exposed to test inputs, thereby no any additional augmented description code of the electrical circuit under analyzing will be generated and no any additional dump file(s) will be generated.
Another object of the present invention is to provide a method and system for analyzing the test coverage of a software model when exposed to test inputs, thereby there is no need to use a simulation software or hardware tool in analyzing the test coverage.
Yet another object of the present invention is to provide a method and system for analyzing test coverage of a software model when exposed to test inputs, thereby the time consumption in analyzing the test coverage is relatively shorter than that by the prior art method.
To achieve the above and other objects, a method is provided for determining test coverage of an original high level language description which represents an electrical circuit by the data of at least one dump file exported by a simulation program, the original high level description having at least one executable assignment statement which models the circuit, the at least one executable assignment statement having a left side and a right side separated by an assignment operator, the left side being a variable, and the right side being an expression which has a set of at least one variable and at least one logic operator, the expression on the right side, when evaluated, determining a value to be assigned to the variable on the left side, the data of the dump file consisting of the values of all the variables of the original high level language description between a simulation start time instant and a simulation end time instant, the method comprising: a description importing step for importing the original high level language description to form a design database; a dump file importing step for importing the dump file; and a test coverage determining step for determining the test coverage of the original high level language description by the values of the variables at all the time instants from the simulation start time instant to the simulation end time instant.